1. Field of the Invention
The present invention relates to a NAND flash memory array and methods for operating and fabricating the same, and more particularly to a NAND flash memory array having a cut-off gate line under a control gate in order to operate two vertical channels independently with one control gate (i.e., a shared word line).
2. Description of the Related Art
These days, flash memories as non-volatile memories have been becoming popular. A conventional flash memory is classified as code flash and data flash according to its application. The code flash memory uses a NOR type structure flash memory having a short random access time, and the data flash memory uses a NAND type structure flash memory having a short writing time and a high integrity.
Particularly, NAND type flash memories, which have a high integrity because it is unnecessary to form contacts of source and drain on each cell, have been used mainly as large capacity storages in portable disks, digital cameras, video recorders, audio recorders and so on. As times have gone by, demands for NAND type flash memories have been increased.
Therefore, a reduction in cell size and electrical power consumption and a high speed operation have been needed to meet an increase in consumption for NAND flash memories.
Up to now, attempts to promote the degree of integrity of NAND flash memory arrays have been focused mainly on the reduction in cell size, based on planar structure. As a result from such attempts having problems with cell operation, there have been some limitations in improving integrity degree.
Therefore, manufacturers pass over memory arrays having conventional planar structures like FIG. 1, and try rather to develop memory arrays having three-dimensional structures, in which embody memory cells by forming trenches on a silicon substrate and using sidewalls of the trenches.
The memory arrays having three-dimensional structures, as shown in FIG. 2, embody word lines on sidewalls as if one crushed the memory array having conventional planar structures into folded array. The three-dimensional structure enables to reduce required areas of total array to a great amount and produce high integrity.
The representative prior arts using the three-dimensional structure were described in U.S. Pat. No. 6,878,991 B1 and Korean patent number 777016 of the same inventors of the present invention.
The latter had an advantage of putting the former invention to practical use, however, as shown in FIG. 3, it should still form a control gate 150 in each cell and has limitation in improving integrity degree.